Prior to describing the present invention, the outline of a conventional semiconductor testing apparatus will be described with reference to FIG. 6.
As shown in FIG. 6, a semiconductor testing apparatus 1 which sets a semiconductor integrated circuit (device under test: DUT) 10 as a test target comprises: as the main components, a test processor (not shown) for controlling the whole semiconductor testing apparatus 1; a pattern generator 11 for generating a test pattern, an expected value pattern or the like; a waveform shaper 12 for shaping the test pattern from the pattern generator 11 into a test signal waveform; a driver circuit 13 for sending the test signal waveform shaped in the waveform shaper 12 to the DUT 10; a pattern comparator 15 for logically comparing a test result sent from the DUT 10 via a comparator 14 with the expected value pattern from the pattern generator 11 to detect whether they correspond to each other in order to judge whether the DUT 10 is acceptable; a timing generator 20 for generating a timing pulse signal and then applying the timing pulse signal to the waveform shaper 12, the comparator 14, the pattern comparator 15, etc. to set the timing of a test; a trigger signal output circuit 40 for outputting a trigger signal to the pattern generator 11 and the timing generator 20, etc.
Among these components, the timing generator 20 generates a clock to which a predetermined delay time has been given from reference timing, and outputs this clock as a timing pulse signal.
The configuration and operation of this timing generator 20 will be explained with reference to FIGS. 7 and 8.
It is to be noted that, in this explanation, a “setting 1” includes RATE 4.8 [ns] and CLK 3.3 [ns], a “setting 2” includes RATE 7.5 [ns] and CLK 4.0 [ns], and a “setting 3” includes RATE 18.0 [ns] and CLK 1.0 [ns], as shown in (a) and (b) in FIG. 8.
Moreover, the period of a reference clock (REFCLK) is 4 [ns] ((c) in FIG. 8).
A RATE signal sends “H” for one DATA RATE with the resolution of a basic period and with the timing of the start of RATE ((d) in FIG. 8).
A RATE setting (RATE high resolution data) for the basic period or less is written in advance in a rate memory 21, and output in response to an address signal (TS signal) of a memory synchronous with the RATE signal.
It is to be noted that the high resolution data is added to the RATE signal in real time, and the RATE signal is shifted one cycle and input to a period counter (COUNTER) 22 when a carry emerges.
In response to the RATE signal, “#0” is loaded into the period counter 22 synchronously with REFCLK, and the period counter 22 counts REFCLK ((e) in FIG. 8).
In a timing memory 23, delay data which is the integral multiple of the REFCLK period has been written in a high order (MSB), and delay data equal to or less than the REFCLK period has been written in a low order (LSB), and they are output in response to the address signal (TS signal) of the memory synchronized with the RATE signal.
The high order of the timing memory 23 and the period counter 22 correspond to each other in all bits, and CLKENB data penetrating REFCLK is only output at a cycle where they correspond to each other ((e), (f) and (g) in FIG. 8).
The output of the rate memory 21 is added to data of a previous cycle in real time, and period components equal to or less than the REFCLK period of the RATE signal are generated as data ((h), (i) and (j) in FIG. 8).
It is to be noted that dotted arrows in FIG. 8 signify additions.
Moreover, addition is continued for the data of the rate memory since the start of an operation, and fractions of the RATE settings are calculated in real time.
Furthermore, lower bits of the timing memory 23 are added to the data, and the carry is used as a control signal for delaying a CLKENB signal ((k) in FIG. 8) for one cycle, and then the result of the addition is coupled with the phase of the data (via a FIFO 24) for use as a control signal of a delay circuit (FINE VD1) 25-1 and a delay circuit (FINE VD2) 25-2 (hereinafter collectively referred to as a “delay circuit 25”.) ((l) and (m) in FIG. 8).
The delay circuit 25 has the same variable amount as that of the REFCLK period, and adds a delay in real time in accordance with the control signal of the delay circuit 25.
Meanwhile, in the timing generator 20, a power supply may be divided so that electricity is supplied to the delay circuit 25 from another system in order to prevent the wraparound of power supply noise generated in logic circuits of the memory, the counter, etc.
In this case, the electric power consumption of the delay circuit 25 can be interpolated to always keep in the vicinity of the maximum electric consumption current regardless of operation modes.
For this interpolation of the electric power, various techniques have heretofore been proposed.
For example, as shown in FIG. 7, a dummy circuit (FINE VD1 (Dummy)) 26-1 and a dummy circuit (FINE VD2 (Dummy)) 26-2 (hereinafter collectively referred to as a “dummy circuit 26”.) that have the same electric power consumption are laid out in the vicinity of the delay circuit 25, and when REFCLK is penetrated by the inversion logic of the CLKENB data, the electric power consumption can be interpolated (e.g., refer to Patent document 1, first prior art.).
Furthermore, because a circuit which propagates the high resolution data for controlling the delay amount of the delay circuit 25 in real time is also laid out on the periphery of the delay circuit 25, there has also been proposed the interpolation of the electric power consumption by the combination of a control circuit (heater control circuit 27) shown in FIG. 9 and a heater circuit 28 shown in FIG. 10.
Still further, there has also been a proposal to use the heater circuit 28 shown in FIG. 10 instead of the dummy circuit 26 shown in FIG. 7 (see FIG. 11, second prior art.).
Further yet, as shown in FIG. 12, there has also been a proposal using the heater circuits 28 and heater control circuits 29 (e.g., refer to Patent document 2, third prior art.). In this configuration, the heater control circuits 29 is provided to detect the front edge and rear edge of an input pulse and the front edge and rear edge of an output pulse of a pulse signal which is input to, propagated through and output from the delay circuit (CMOS circuit), and thus output a front edge passage period signal and a rear edge passage period signal. There are disposed, in the vicinity of the CMOS circuit, a front edge compensation heater 28-1 for always passing a constant consumed current when no pulse signal is present, and shutting off the constant consumed current only during a period in which the front edge passage period signal is received, and a rear edge compensation heater 28-2 for shutting off the constant consumed current only during a period in which the rear edge passage period signal is received.
Patent document 1: Japanese Patent Publication Laid-open No. 8-330920
Patent document 2: Japanese Patent Publication Laid-open No. 11-074768